1. Field of the Invention
The present invention relates generally to transistor configurations and in particular to circuitry which includes matched bipolar transistor pairs.
2. Description of Related Art
Transistor matching is important for improved operation for many types of integrated circuits. Referring to the drawings, FIG. 1 shows circuitry which includes an ideal operational amplifier A. A non-ideal operational amplifier will posses a finite input offset voltage Vos which can be defined as the magnitude of the input voltage difference necessary to provide a zero output. The FIG. 1 circuit is a model illustrating the effect of input offset voltage Vos on an amplifier having a typical feedback network comprising Zi and Zf. The effect of Vos on the output voltage Vo for the FIG. 1 configuration is as follows:Vo=Vos(Zf+Zi)/Zi  Eq (1).
Clearly there is an incentive to reduce the influence of the input offset voltage Vos since it results in an error in the output voltage Vo.
Amplifier A of FIG. 1 typically includes a differential input stage having differential inputs (−) and (+). FIG. 2A is a portion of a simplified differential input stage 22A which includes a differential transistor pair Q1 and Q2. The base electrodes of Q1 and Q2 form the respective differential inputs (+) and (−) of the amplifier, with the emitters of the pair being coupled to a common tail current source. Note that in some applications, emitter resistors RE can be made smaller or close to zero. The tail current source includes a transistor Q0 having a base connected to a bias voltage Vbias and an emitter connected to ground. The tail current source provides a relatively constant current output which is divided between Q1 and Q2, with the magnitude of the division depending upon the relative magnitudes that form the differential inputs (+) and (−). For large signal differential inputs it is possible that one transistor will be turned off and with the other transistor will be conducting the entire current from source transistor Q0. However, for small signal differential inputs, a differential current is produced in Q1 and Q2 relating to the differential input.
FIG. 2B is another differential input stage 22B which is electrically equivalent to the input stage of FIG. 2A assuming that the total current produced by QA and QB is the same as the current provided by Q0.
As used herein, the term “differential transistor pair circuitry” is defined to mean a pair of transistors arranged in a differential circuit configuration such that a small signal differential input applied between the transistor base electrodes results in a differential current flow in the transistors. By way of example, transistors Q1 and Q2 of FIG. 2A form differential transistor pair circuitry as do transistors Q1 and Q2 of FIG. 2B.
A major source of input offset voltage Vos for a typical operational amplifier is due to a mismatch between the differential input pair such a transistor pair Q1/Q2. When the input pair transistors are conducting equal currents, the base-emitter voltages VBE of the two transistors are ideally the same. Any differences in VBE voltage will result in a corresponding input offset voltage Vos for the associated amplifier.
Transistor mismatches are relevant to circuitry other than differential transistor pairs. FIG. 9A shows a typical current mirror circuit 24 made up of matched transistors Q3 and Q4. The term matched in this context means that for equal emitter current densities, two matched transistors will produce the same base-emitter voltages VBE. As can be seen in FIG. 9A, the base electrodes of Q3 and Q4 are connected together as are the emitter electrodes (both connected to the circuit common). Transistor Q3, which is this example is connected like a diode will conduct a current based essentially upon the voltage dropped across resistor 26 which is equal to (+Vcc−VBE)/R where R is the value of resistor 26. This current, which forms the input of the current mirror, will produce a resultant base-emitter voltage VBE across Q3 which will also be dropped across the base-emitter electrodes of Q4. Assuming that Q3 and Q4 have equal emitter areas, this base-emitter voltage will result in a current through Q4 which is equal to that in Q3. Frequently, the emitter areas of either Q3 or Q4 or both are adjusted to provide differing current mirror values. By way of example, if the emitter area of Q3 were twice that of Q4, Q4 would conduct twice the current of Q3. In order to provide a more precise emitter area ratio of two, transistor Q3 could be formed from two transistors similar to Q4, with the two transistors being connected in parallel so as to result in an effective single transistor having twice the emitter area of Q4.
Note that the above-described relationship between the two currents in the FIG. 9A current mirror circuit ignores various sources of errors. That includes errors which result from the fact that Q3 and Q4 may not have the same base-collector voltages (errors due to the Early effect) and the fact that both transistors draw base currents (the current gains are finite). However, variations of the FIG. 9A circuitry have been developed to address these sources of current mirror errors. Even if these sources of errors are addressed, the base-emitter regions of transistors Q3 and Q4 could still be mismatched such that equal base-emitter voltages VBE do not result in equal current densities. This, this mismatch will result in current mirror circuit errors in current magnitudes.
FIG. 9B shows another prior art current mirror circuit 25 similar to circuit 24 of FIG. 9A with transistor Q4A of FIG. 9B being the same as Q4. In this case, an additional transistor Q4B is added to the circuit, with Q4B typically being identical to Q4A so that Q4A and Q4B conduct the same current. However, mismatching between Q4A and Q4B can further result in differences in the current magnitudes of the two transistors.
As used herein, the term “current mirror transistor pair circuitry” is defined to mean a pair of transistors arranged in a current mirror configuration having a common base connection, separate collector connections and the same respective emitter current densities. By way of example, transistors Q3 and Q4 of FIG. 9A form current mirror transistor pair circuitry. As another example, transistors Q4A and Q4B of FIG. 9B also form current mirror transistor pair circuitry.
Still another circuit that can suffer from transistor mismatch is the prior art band-gap reference circuit such as depicted in FIG. 10A. As is well known, a band-gap reference circuit provides a temperature compensated reference voltage Vref. The circuit operates to combine two voltages having opposite temperature coefficients (tempcos) which are combined to provide a reference voltage with a near zero tempco. The base-emitter voltage VBE of a silicon transistor has a magnitude at room temperature of about 600 mV and a negative tempco of approximately −2 mV/° C. A difference in base-emitter voltages ΔVBE which results from a difference in current density of 10 to 1 is about 60 mV, with this voltage having a positive tempco of approximately +0.085 mV/° C. When these two voltage components are properly scaled and combined the desired low tempco reference voltage is produced.
Referring again to the FIG. 10A reference circuit, transistor Q5 is configured to operate at a higher current density than transistor Q6. This is typically achieved by making currents I1 and I2 equal to one another and forming Q6 to have an emitter area larger than that of Q5. Of course, the magnitudes of the currents can also be adjusted. If the emitter area ratio is 10 to 1 for example, the difference in base-emitter voltages ΔVBE of Q5 and Q6 is about 60 mV at room temperature. That difference in voltage is dropped across resistor 34 which produces a current I2 in transistor Q6 also having a positive tempco. The ratio of resistors 34 and 36 provide a scaling factor of 1 to 10 so that the positive tempco voltage across resistor 36 is about 600 mV. The reference output voltage Vref is the sum of the base-emitter voltage VBE of Q7 and the ΔVBE voltage dropped across resistor 36 to provide a total near zero tempco voltage of about 1.2 V. The accuracy of the FIG. 10A band-gap reference circuit over temperature is highly dependent upon the accurate matching of transistors Q5 and Q6 which produce the ΔVBE term, other than ratio of resistances 36 and 38.
FIG. 10B depicts another band-gap reference circuit. Resistors 42 and 44 are usually the same value. Feedback operation of operational amplifier 46 functions to maintain the voltage levels at the amplifier inputs at the same magnitude so that currents I1 and I2 are equal. Transistor Q8 has an emitter area which is larger than that of Q9, with a ratio of 10 to 1 being typical. Thus, transistor Q8 has a base-emitter voltage which is about 60 mV less than the base-emitter voltage of Q9 so that a ΔVBE term is dropped across resistor 48. The values of resistors 48 and 50 are selected to scale the 60 mV drop across resistor 48 to about 600 mV, with this voltage having a positive tempco. That voltage is added to the base-emitter voltage VBE of Q9 to provide a near zero tempco output reference voltage Vref of about 1.2 volts. Once again, the matching of transistors Q8 and Q9 is a major factor in the accuracy of Vref.
FIG. 10C shows a still further band-gap reference circuit which includes matched transistors Q10 and Q11. Transistor Q10 typically has an emitter area ratio with respect to transistor Q11 of 10 to 1. Once again, operational amplifier 58 operates to maintain through feedback equal voltages at the amplifier inputs so that the voltage drops across resistors 52 and 54 are equal. Assuming that the values of resistors 52 and 54 are equal, currents I1 and I2 provided to transistors Q10 and Q11 are also equal. Thus, the base-emitter voltage VBE of Q10 is about 60 mV less than that of Q11 so that a ΔVBE of that value is dropped across resistor 56. The positive tempco voltage is scaled up to about 600 mV based upon the values of resistors 52 and 56. The negative tempco base-emitter voltage VBE of Q10 is added to the positive tempco voltage across resistors 52 and 56 to provide the near zero tempco output voltage Vref of 1.2 volts. Once again, the matching of transistors Q10 and Q11 is a major factor in the accuracy of voltage Vref.
As used herein, the term “voltage reference transistor pair circuitry” is defined to mean a pair of transistors arranged in a voltage reference configuration where the reference output is derived from the combination of a negative tempco component and a positive tempco component, with the positive tempco component being derived from a difference in base-emitter voltages of the transistor pair. By way of example, transistors Q5 and Q6 of FIG. 10A form voltage reference transistor pair circuitry as do transistors Q8 and Q9 of FIG. 10B and transistors Q10 and Q11 of FIG. 10C.
Although various techniques have been used to enhance the matching of the above-described differential, current mirror and voltage reference differential transistor pair circuitry, there is room for improvement as will be described in the following Detail Description of the Invention taken together with the drawings.